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kernel/3081: DLINK DFE580TX driver broken, VLAN problem + other stuff
From: box <box(at)xbsd.dk>
Date: Tue Feb 04 2003 - 15:30:27 EST
System : OpenBSD 3.1 Architecture: OpenBSD.i386 Machine : i386 >Description: Either the driver, or the hardware sucks... really sucks. The DLINK 570TX was an ok NIC, but this is really bad. But here goes: VLAN not supported, see patch. Multicast not supported, see patch, not a good solution, but the MAC is programmed incorrectly I think (ipv6 multicast mac addresses??) Two PHY's found per interface, but why? Keep getting underrun errors, see patch. Not good enough but gets you going. Changing MTU not supported, see patch >Fix: Below is the patch I use to get things going, all of it might not be good, it gets me going. "Fixes" multicast filters as well, but it's not the rigth solution, but i think that the problem with the filters is that only ipv6 mac address's are programmed into the MAC. The threshhold code has been modified as well, speeds things up a bit... not nescecarilly good! "Fixes" the why two phy's per MAC? problem...
#include "bpfilter.h"
#include <sys/param.h>
+#if NVLAN > 0 +#include #include <net/bpf.h> #endif @@ -334,6 +340,9 @@ {
struct ste_softc *sc = (struct ste_softc *)self;
struct ste_mii_frame frame;
+
+ if ( sc->ste_one_phy && phy != 0 )
+ return (0);
bzero((char *)&frame, sizeof(frame));
@@ -531,6 +540,7 @@
if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
+ STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLIPMULTI);
return;
}
@@ -553,6 +563,7 @@
CSR_WRITE_4(sc, STE_MAR1, hashes[1]);
STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
+ STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLIPMULTI);
return;
} @@ -733,7 +744,7 @@
if (txstat & STE_TXSTATUS_UNDERRUN &&
sc->ste_tx_thresh < STE_PACKET_SIZE) {
- sc->ste_tx_thresh += STE_MIN_FRAMELEN;
+ sc->ste_tx_thresh += (4 * STE_MIN_FRAMELEN);
printf("ste%d: tx underrun, increasing tx"
" start threshold to %d bytes\n",
sc->ste_unit, sc->ste_tx_thresh);
@@ -871,6 +882,10 @@
s = splimp();
sc->ste_unit = sc->sc_dev.dv_unit;
+ /* If RevisionID = 0x12 it's a DLINK 580TX and we should only probe one PHY */
+ if ((pci_conf_read(pc, pa->pa_tag, STE_PCI_REVISION_ID) & 0x000000FF) == 0x12)
+ sc->ste_one_phy = 1;
+
/*
* Handle power management nonsense.
*/
@@ -988,6 +1003,10 @@
IFQ_SET_READY(&ifp->if_snd);
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
+#if NVLAN > 0
+ ifp->if_capabilities |= IFCAP_VLAN_MTU;
+#endif
+ sc->sc_mii.mii_ifp = ifp; sc->sc_mii.mii_readreg = ste_miibus_readreg; sc->sc_mii.mii_writereg = ste_miibus_writereg; @@ -1001,6 +1020,8 @@ } else ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); + sc->ste_tx_thresh = 240; + /* * Call MI attach routines. */ @@ -1047,7 +1068,7 @@ c->ste_mbuf = m_new; c->ste_ptr->ste_status = 0; c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); - c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; + c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST; return(0); }
@@ -1212,6 +1233,9 @@
CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
+ /* Accept VLAN length packets */
+ CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN);
+
ste_ifmedia_upd(ifp);
ifp->if_flags |= IFF_RUNNING;
@@ -1343,6 +1367,13 @@
sc->ste_if_flags = ifp->if_flags;
error = 0;
break;
+ case SIOCSIFMTU:
+ if(ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) {
+ error = EINVAL;
+ } else if (ifp->if_mtu != ifr->ifr_mtu) {
+ ifp->if_mtu = ifr->ifr_mtu;
+ }
+ break;
case SIOCADDMULTI:
case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
@@ -1466,7 +1497,7 @@
sc->ste_cdata.ste_tx_prod = idx;
start_tx->ste_prev->ste_ptr->ste_next = start_tx->ste_phys;
- ifp->if_timer = 5;
+ ifp->if_timer = 10;
return;
}
--- if_stereg.h.org Sun Dec 1 15:38:24 2002
+++ if_stereg.h Sun Dec 1 15:39:46 2002
@@ -353,6 +353,7 @@
#define STE_PCI_DEVICE_ID 0x02
#define STE_PCI_COMMAND 0x04
#define STE_PCI_STATUS 0x06
+#define STE_PCI_REVISION_ID 0x08
#define STE_PCI_CLASSCODE 0x09
#define STE_PCI_LATENCY_TIMER 0x0D
#define STE_PCI_HEADER_TYPE 0x0E
@@ -514,6 +515,7 @@
struct ste_list_data *ste_ldata;
caddr_t ste_ldata_ptr;
struct ste_chain_data ste_cdata;
+ u_int8_t ste_one_phy;
}; struct ste_mii_frame { >Release-Note:
This archive was generated by hypermail 2.1.8 : Wed Aug 23 2006 - 13:29:50 EDT |
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