kernel/3374: support for VIA VT6103 PHY

From: <matthew.gream(at)pobox.com>
Date: Mon Jul 28 2003 - 15:36:50 EDT

>Number:         3374
>Category:       kernel
>Synopsis:       support for VIA VT6103 PHY
>Confidential:   yes
>Severity:       non-critical
>Priority:       low
>Responsible:    bugs
>State:          open
>Quarter:        
>Keywords:       
>Date-Required:
>Class:          change-request
>Submitter-Id:   net
>Arrival-Date:   Mon Jul 28 19:50:02 GMT 2003
>Closed-Date:
>Last-Modified:
>Originator:     Matthew Gream
>Release:        3.3-stable
>Organization:
>Environment:
	System      : OpenBSD 3.3
	Architecture: OpenBSD.i386
	Machine     : i386
>Description:
	Support the VIA VT6103 PHY as found on the VIA EPIA 5000 motherboard.
>How-To-Repeat:
	Boot on VIA device
>Fix:
	patch supplied (no brainer version of ukphy)

Index: files.mii

---

RCS file: /cvs/src/sys/dev/mii/files.mii,v retrieving revision 1.19
diff -u -r1.19 files.mii

--- files.mii	7 May 2002 19:31:16 -0000	1.19


+++ files.mii	28 Jul 2003 19:33:29 -0000

@@ -89,6 +89,10 @@
 attach xmphy at mii
 file dev/mii/xmphy.c xmphy  

+device vrphy: mii_phy
+attach vrphy at mii
+file dev/mii/vrphy.c vrphy
+

 device amphy: mii_phy
 attach amphy at mii
 file dev/mii/amphy.c amphy
Index: miidevs

---

RCS file: /cvs/src/sys/dev/mii/miidevs,v retrieving revision 1.33
diff -u -r1.33 miidevs

--- miidevs	19 Feb 2003 10:12:55 -0000	1.33


+++ miidevs	28 Jul 2003 19:33:30 -0000


@@ -59,6 +59,7 @@
 oui SIS				0x00e006	Silicon Integrated Systems
 oui TI				0x080028	Texas Instruments
 oui TSC				0x00c039	TDK Semiconductor


+oui VIA			0x004063	VIA Technologies Inc.


 oui XAQTI			0x00e0ae	XaQti Corp.
 

 /* in the 79c873, AMD uses another OUI (which matches Davicom!) */ @@ -177,6 +178,9 @@
 /* TDK Semiconductor PHYs */

 model TSC 78Q2120		0x0014 78Q2120 10/100 media interface
 model TSC 78Q2121		0x0015 78Q2121 100baseTX media interface

+
+/* VIA Technologies Inc. PHYs */
+model VIA VT6103 0x0032 VIA VT6103 10/100 PHY
 

 /* XaQti Corp. PHYs */
 model XAQTI XMACII 0x0000 XaQti Corp. XMAC II gigabit interface Index: miidevs.h

---

RCS file: /cvs/src/sys/dev/mii/miidevs.h,v retrieving revision 1.36

diff -u -r1.36 miidevs.h
--- miidevs.h	19 Feb 2003 10:13:05 -0000	1.36


+++ miidevs.h	28 Jul 2003 19:33:30 -0000


@@ -1,4 +1,4 @@
-/*	$OpenBSD: miidevs.h,v 1.36 2003/02/19 10:13:05 miod Exp $	*/


+/*	$OpenBSD$	*/


 

 /*

• THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. @@ -66,6 +66,7 @@ #define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */ #define MII_OUI_TI 0x080028 /* Texas Instruments */ #define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */
  +#define MII_OUI_VIA 0x004063 /* VIA Technologies Inc. */
  #define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */

 /* in the 79c873, AMD uses another OUI (which matches Davicom!) */ @@ -235,6 +236,10 @@

 #define	MII_STR_TSC_78Q2120	"78Q2120 10/100 media interface"
 #define	MII_MODEL_TSC_78Q2121	0x0015
 #define	MII_STR_TSC_78Q2121	"78Q2121 100baseTX media interface"

+
+/* VIA Technologies Inc. PHYs */
+#define MII_MODEL_VIA_VT6103 0x0032
+#define MII_STR_VIA_VT6103 "VIA VT6103 10/100 PHY"
 

 /* XaQti Corp. PHYs */
 #define MII_MODEL_XAQTI_XMACII 0x0000
Index: vrphy.c

---

RCS file: vrphy.c
diff -N vrphy.c

--- /dev/null	1 Jan 1970 00:00:00 -0000


+++ vrphy.c	28 Jul 2003 19:33:30 -0000


@@ -0,0 +1,178 @@

+/*	$OpenBSD: vrphy.c,v 1.4 2002/04/17 19:30:26 jason Exp $	*/

+
+/*
+ * Copyright (c) 2003
+ * Matthew Gream <matthew.gream@pobox.com>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/mii/vrphy.c,v 1.3 2000/04/19 14:57:29 phk Exp $
+ */
+
+/*
+ * Driver for VIA VT6103 PHYs
+ * Based upon VIA "VT6103 - Fast Ethernet 10 / 100 PHY / Transceiver",
+ * Revision 1.1, April 15, 2002.
+ */
+
+#include <sys/param.h>
Index: vrphyreg.h

---

RCS file: vrphyreg.h
diff -N vrphyreg.h

--- /dev/null	1 Jan 1970 00:00:00 -0000


+++ vrphyreg.h	28 Jul 2003 19:33:30 -0000


@@ -0,0 +1,115 @@

+/*	$OpenBSD: vrphyreg.h,v 1.1 2000/10/17 15:59:10 jason Exp $	*/

+
+/*
+ * Copyright (c) 2003
+ * Matthew Gream <matthew.gream@pobox.com>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD: src/sys/dev/mii/vrphyreg.h,v 1.1 1999/09/06 05:27:55 wpaul Exp $
+ */
+
+#ifndef _DEV_MII_VRPHYREG_H_
+#define _DEV_MII_VRPHYREG_H_
+
+/*
+ * VIA VT6103 registers.
+ */
+
+#define MII_VRPHY_CFG1 0x10
+#define CFG1_PHY_ADDRESS 0xF800 /* PHY Address (def = 01) */
+#define CFG1_FIBERMODE 0x0400 /* Fiber Mode (def = 0) */
+#define CFG1_CABLETYPE 0x0200 /* Cable Type 0=UTP5/STP 100ohm (def), 1=STP 150ohm */
+#define CFG1_FORCEPHY 0x0100 /* Force PHY in Link Good Status (def = 0) */
+#define CFG1_10XSQUEL 0x0080 /* Base10Tx Low Squelch Level Select (def = 0) */
+#define CFG1_LEDOSEL 0x0060 /* Progammable LED Output Select (def = 00) */
+#define CFG1_RPTRMODE 0x0010 /* Repeater mode (def = 0) */
+#define CFG1_INTRSEL 0x0008 /* 0 = INT# (def), 1 = MDIO */
+#define CFG1_SYMBOLMODE 0x0004 /* Symbol Mode (RO) (def = 0) */
+
+#define MII_VRPHY_CFG2 0x11
+#define CFG2_JABDET 0x8000 /* Jabber Detect (def = 1) */
+#define CFG2_SQEDET 0x4000 /* Signal Quality Error Detect (def = 1) */
+#define CFG2_AUPCOR 0x2000 /* Auto-Polarity Correction (def = 1) */
+#define CFG2_FEFD 0x1000 /* Far End Fault Detect (def = 1) */
+#define CFG2_CHSPEED 0x0800 /* Change Speed [self clearing] (def = 0) */
+#define CFG2_SEED 0x07FF /* Seed (def = 7FF) */
+
+#define MII_VRPHY_CFG3 0x12
+#define CFG3_BYSCR 0x8000 /* Bypass Scramber and Descrambler Functions (def = 0) */
+#define CFG3_BY4B5B 0x4000 /* Bypass 4B5B Encoding and Decoding Functions (def = 0) */
+#define CFG3_BYSYM 0x1000 /* Bypass Symbol Alignment Function (def = 0) */
+#define CFG3_LOSYNC 0x0800 /* Loss Sync Function [self clearing] (def = 1) */
+#define CFG3_LOSYNCTM 0x0400 /* Lost Sync Timer Select 0=722us, 1=2ms (def = 0) */
+#define CFG3_RESERVED 0x03FF /* Reserved (def = 0) */
+
+#define MII_VRPHY_CFG4 0x13
+#define CFG4_MASKINTR 0x8000 /* Mask Interrupt Function (def = 1) */
+#define CFG4_MASKINTRLNKUP 0x4000 /* Mask Interrupt on Link-Up Status (def = 1) */
+#define CFG4_MASKINTRLNKFAIL 0x2000 /* Mask Interrupt on Link-Fail Status (def = 1) */
+#define CFG4_MASKINTRLNKCHNG 0x1000 /* Mask Interrupt on Link Status Change (def = 1) */
+#define CFG4_MASKINTRAUTCOMP 0x0800 /* Mask Interrupt on Auto-Negotiation Process Complete (def = 1) */
+#define CFG4_MASKINTRPAGERCV 0x0400 /* Mask Interrupt on Page Received in Auto-Negotiation Process (def = 1) */
+#define CFG4_MASKINTRJABDET 0x0200 /* Mask Interrupt on Jabber Condition Detect (def = 1) */
+#define CFG4_MASKINTRINVSYM 0x0100 /* Mask Interrupt on Invalid Symbol Received (def = 1) */
+#define CFG4_MASKINTRSSDDELM 0x0080 /* Mask Interrupt on SSD Error Detected (def = 1) */
+#define CFG4_MASKINTRESDDELM 0x0040 /* Mask Interrupt on ESD Error Detected (def = 1) */
+#define CFG4_MASKINTRSQEDET 0x0020 /* Mask Interrupt on Signal Quality Error Detected (def = 1) */
+#define CFG4_MASKINTRLNKFMAX 0x0010 /* Mask Interrupt on Link Fail Counter in Rx15 Count to Max (def = 1) */
+#define CFG4_MASKINTRINVSMAX 0x0008 /* Mask Interrupt on Invalid Symbol Received in Rx16 Count to Max (def = 1) */
+#define CFG4_MASKINTRFALCMAX 0x0004 /* Mask Interrupt on False Carrier Counter in Rx17 Count to Max (def = 1) */
+#define CFG4_RESERVED 0x0003 /* Reserved (def = 0) */
+
+#define MII_VRPHY_STATUS 0x14
+#define STAT_POLINV 0x8000 /* Polarity Inversion Base10-Tx */
+#define STAT_LNKUP 0x4000 /* Link-Up Status */
+#define STAT_LNKFAIL 0x2000 /* Link-Fail Status */
+#define STAT_LNKCHNG 0x1000 /* Link Status */
+#define STAT_AUTCOMP 0x0800 /* Auto-Negotiation Process Complete */
+#define STAT_PAGERCV 0x0400 /* Page Received in Auto-Negotiation Process */
+#define STAT_JABDET 0x0200 /* Jabber Condition Detect */
+#define STAT_INVSYM 0x0100 /* Error Code Symbol Received */
+#define STAT_SSDDELM 0x0080 /* SSD Error */
+#define STAT_ESDDELM 0x0040 /* ESD Error */
+#define STAT_SQEDET 0x0020 /* SQE Error */
+#define STAT_LNKFMAX 0x0010 /* Link Fail Counter in Rx15 Count to Max */
+#define STAT_INVSMAX 0x0008 /* Invalid Symbol Received in Rx16 Count to Max */
+#define STAT_FALCMAX 0x0004 /* False Carrier Counter in Rx17 Count to Max */
+#define STAT_PHYSPEED 0x0002 /* PHY Speed Status */
+#define STAT_PHYDUPLX 0x0001 /* PHY Duplex Status */
+
+#define MII_VRPHY_LINKFAILCTR 0x15 /* Link Fail Counter */
+
+#define MII_VRPHY_SYMERRCTR 0x16 /* Count of Invalid Symbols Received (Speed 100) */
+#define MII_VRPHY_JABBERCTR 0x16 /* Jabber Detect Count (Speed 10) */
+
+#define MII_VRPHY_FALSECARCTR 0x17 /* False Carrier Count (Speed 100) */
+#define MII_VRPHY_SQEDETECTCTR 0x17 /* SQE Detect Count (Speed 10) */
+
+
+#endif /* _DEV_MII_VRPHYREG_H_ */

>Release-Note:
>Audit-Trail:
>Unformatted:

Received on Mon Jul 28 16:12:14 2003